A Substrate-Plate Trench-Capacitor (SPT) Memory Cell for Dynamic RAM's
- Nicky Chau-Chun Lu
- Tak H. Ning
- et al.
- 1986
- IEEE Journal of Solid-State Circuits
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224 results at IEEE Journal of Solid-State Circuits
32K READ-ONLY-MEMORY CHIP DESIGN IN JOSEPHSON TECHNOLOGY: A FEASIBILITY STUDY.
- H. Beha
- 1986
- IEEE Journal of Solid-State Circuits
DESIGN-PERFORMANCE TRADE-OFFS IN CMOS-DOMINO LOGIC.
- Vojin G. Oklobdzija
- Robert K. Montoye
- 1986
- IEEE Journal of Solid-State Circuits
A TDI Charge-Coupled Imaging Device for Page Scanning
- Eugene S. Schlig
- 1986
- IEEE Journal of Solid-State Circuits
Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's
- Nicky C. C. Lu
- Hu H. Chao
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
Performance Limits of CMOS ULSI
- James R. Pfiester
- John D. Shott
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
Stability and SER Analysis of Static RAM Cells
- Barbara Chappell
- Stanley E. Schuster
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
A Self-Aligned 1-μm-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy
- Yuan Taur
- Genda J. Hu
- et al.
- 1985
- IEEE Journal of Solid-State Circuits
A 20 ns 64K (4K X16) NMOS RAM
- Stanley E. Schuster
- Barbara Chappell
- et al.
- 1984
- IEEE Journal of Solid-State Circuits
Half-VDD Bit-Line Sensing Scheme in CMOS DRAM's
- Nicky Chau-Chun Lu
- Hu H. Chao
- 1984
- IEEE Journal of Solid-State Circuits