Publications

2 results at IEDM 2025

Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- - Nick Lanzillo
  - Jim Mazza
  - et al.
- 2025
- IEDM 2025
Transfer Learning on Edge Using 14nm CMOS-compatible ReRAM Array and Analog In-memory Training Algorithm
- - Takashi Ando
  - Omobayode Fagbohungbe
  - et al.
- 2025
- IEDM 2025