A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFETDanny LuuLukas Kullet al.2017VLSI Circuits 2017
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFETLukas KullDanny Luuet al.2017ISSCC 2017
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFETAlessandro CevreroIlter Ozkayaet al.2017ISSCC 2017
Modeling and Pareto Optimization of On-Chip Switched Capacitor ConvertersToke M. AndersenFlorian Krismeret al.2017IEEE-TEPL
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power DeliveryToke M. AndersenFlorian Krismeret al.2017IEEE-TEPL
Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmeticMarcel KosselMatthias Braendliet al.2016Electronics Letters
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOSHazar YuekselMatthias Braendliet al.2016ESSCIRC 2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOSLukas KullJ. Plivaet al.2016IEEE JSSC