BBPD with wide input phase range
- Marcel Kossel
- Pier Andrea Francese
- et al.
- 2019
- Electronics Letters
Matthias Brändli
Title
Digital Circuit Design
Publications
30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- ISSCC 2019
6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2019
- ISSCC 2019
A 24-72-GS/s 8-b time-interleaved SAR ADC with 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2018
- IEEE JSSC
A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14-nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2018
- IEEE JSSC
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- Lukas Kull
- Danny Luu
- et al.
- 2018
- VLSI Circuits 2018
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- Pier Andrea Francese
- Alessandro Cevrero
- et al.
- 2018
- VLSI Circuits 2018
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2018
- VLSI Circuits 2018
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2018
- IEEE TCAS-I
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- Gain Kim
- Lukas Kull
- et al.
- 2018
- ISCAS 2018
Patents
- US
- 12095473
- US
- 11816062
- US
- 11057039
- US
- 9496008
Projects
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
TM
Thomas Morf
Senior Research Scientist
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MK
Marcel Kossel
Circuit Designer
MP
Mridula Prathapan
Cryogenic CMOS design for quantum control