Matthias Brändli

Publications

• A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

  • • Gain Kim
    • Marcel Kossel
    • et al.
  • 2020
  • IEEE JSSC

• A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET

  • • Gain Kim
    • Lukas Kull
    • et al.
  • 2019
  • A-SSCC 2019

• BBPD with wide input phase range

  • • Marcel Kossel
    • Pier Andrea Francese
    • et al.
  • 2019
  • Electronics Letters

• 6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET

  • • Alessandro Cevrero
    • Ilter Ozkaya
    • et al.
  • 2019
  • ISSCC 2019

• 30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

  • • Gain Kim
    • Lukas Kull
    • et al.
  • 2019
  • ISSCC 2019

• A 24-72-GS/s 8-b time-interleaved SAR ADC with 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

  • • Lukas Kull
    • Danny Luu
    • et al.
  • 2018
  • IEEE JSSC

• A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14-nm CMOS FinFET

  • • Danny Luu
    • Lukas Kull
    • et al.
  • 2018
  • IEEE JSSC

• A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

  • • Lukas Kull
    • Danny Luu
    • et al.
  • 2018
  • VLSI Circuits 2018

• A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS

  • • Thomas Toifl
    • Christian Menolfi
    • et al.
  • 2018
  • VLSI Circuits 2018

• A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE

  • • Pier Andrea Francese
    • Alessandro Cevrero
    • et al.
  • 2018
  • VLSI Circuits 2018