Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
Matthias Brändli
Title
Digital Circuit Design
Publications
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
CMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
- Marcel Kossel
- Matthias Braendli
- et al.
- 2016
- Electronics Letters
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2016
- IEEE JSSC
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- Hazar Yueksel
- Lukas Kull
- et al.
- 2015
- ESSCIRC 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
Patents
- US
- 12095473
- US
- 11816062
- US
- 11057039
- US
- 9496008
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
TM
Thomas Morf
Senior Research Scientist
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MK
Marcel Kossel
Circuit Designer
CZ
Cezar Zota
Staff Research Scientist, Master inventor