A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Pier Andrea Francese
Title
Principal RSM - Analog Circuit Design
Bio
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Publications
Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2016
- IEEE JSSC
A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path
- 2016
- ISSCC 2016
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- Hazar Yueksel
- Lukas Kull
- et al.
- 2015
- ESSCIRC 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- Alessandro Cevrero
- Cosimo Aprile
- et al.
- 2015
- VLSI Circuits 2015
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2015
- ISSCC 2015
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
- Lukas Kull
- J. Pliva
- et al.
- 2014
- A-SSCC 2014
A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- Gautam R. Gangasani
- Chun-Ming Hsu
- et al.
- 2014
- IEEE JSSC
A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth
- Pier Andrea Francese
- Thomas Toifl
- et al.
- 2014
- IEEE JSSC
Patents
- US
- 12095473
- US
- 12088316
- DE
- 11 2019 000 181
- TW
- I850965
- GB
- 2620314
- KR
- 2672586
- CN
- ZL201980010119.8
- SG
- 11202110345X
- US
- 11916568
- JP
- 7427030
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
MB
Matthias Brändli
Digital Circuit Design
MK
Marcel Kossel
Circuit Designer
TM
Thomas Morf
Senior Research Scientist
CZ
Cezar Zota
Staff Research Scientist, Master inventor