High performance of planar double gate MOSFETs with thin backgate dielectrics

Abstract

Planar double gate CMOS devices with thin silicon channels and electrically separate polysilicon top and bottom gates are fabricated. NFETs with Ldesign= 175nm and 1.3 mA/μm and PFETs with Ldesign= 125nm and 400 μA/μm are achieved at Vdd=1.2V. To our knowledge, this is the largest current yet achieved in double gate NMOS devices. Electrical results show a high quality backgate dielectric, improvement of SCE using the backgate, and the importance of reducing external resistance in short channel devices.