Thermal stability of ultra-thin InGaAs-on-insulator substrates
N. Daix, Lukas Czornomaz, et al.
S3S 2013
We present a tri-gate In0.53Ga0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n-In0.53Ga0.47As channel doped to 1018/cm3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2O3 presents a bandgap of 7.0 eV, a k-value of 8.1 and a breakdown field of 8-10.5 MV/cm. A post-fabrication H2/Ar anneal applied to the PE-ALD Al2O3/In0.53Ga0.47As-OI gate stack yielded a low density of interface traps (Dit) of 7 × 1011/cm2 eV at Ec - E = -0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2O3/HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53Ga0.47As. The H2/Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2/Ar anneal, the long-channel (10 μm) device featured a threshold voltage (VT) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III-V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2/Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.
N. Daix, Lukas Czornomaz, et al.
S3S 2013
Felix Eltes, Daniele Caimi, et al.
IPC 2018
Lukas Czornomaz, N. Daix, et al.
ESSDERC 2013
José P. B. Silva, Ruben Alcala, et al.
APL Materials