A 0.127 μm2 high performance 65 nm SOI based embedded DRAM for on-processor applications
- G. Wang
- K. Cheng
- et al.
- 2006
- IEDM 2006
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12 results for J. Benedict
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
Issues in NiSi-gated FDSOI device integration
- Jakub Kedzierski
- Diane Boyd
- et al.
- 2003
- IEDM 2003
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- M. Yang
- M. Ieong
- et al.
- 2003
- IEDM 2003
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
- Jakub Kedzierski
- Edward Nowak
- et al.
- 2002
- IEDM 2002
High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors
- Charles T. Black
- Kathryn W. Guarini
- et al.
- 2004
- IEEE Electron Device Letters
Cleans for Al vias in a 0.175 μm Dual Damascene Process
- J.P. Gambino
- L. Clevenger
- et al.
- 1999
- IITC 1999
Two gates are better than one
- P. Solomon
- K.W. Guarini
- et al.
- 2003
- IEEE Circuits and Devices Magazine
A 10 nm MOSFET concept
- J. Appenzeller
- R. Martel
- et al.
- 2001
- Microelectronic Engineering
Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors
- J. Appenzeller
- R. Martel
- et al.
- 2000
- Applied Physics Letters