A Fully Scaled Submicrometer NMOS Technology Using Direct-Write E-Beam Lithography
- Matthew R. Wordeman
- April M. Schweighart
- et al.
- 1985
- IEEE T-ED
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80 results for Robert Dennard
CHARACTERIZATION AND MODELING OF A LATCHUP-FREE 1- mu M CMOS TECHNOLOGY.
- Y. Taur
- W.H. Chang
- et al.
- 1983
- IEDM 1983
FULLY SEALED HALF-MICROMETER NMOS TECHNOLOGY USING DIRECT-WIRE E-BEAM LITHOGRAPHY.
- M.R. Wordeman
- A.M. Schweighart
- et al.
- 1983
- VLSI Technology 1983
Evolution of the MOSFET Dynamic RAM—A Personal View
- Robert H. Dennard
- 1984
- IEEE T-ED
Generalized Scaling Theory and Its Application to a 1/4 micrometer MOSFET Design
- Robert H. Dennard
- Matthew R. Wordeman
- 1984
- IEEE T-ED
Physical limits to VLSI technology using silicon MOSFET's
- Robert H. Dennard
- 1983
- Physica B+C
Alpha-Particle-Induced Soft Error Rate in VLSI Circuits
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1982
- IEEE T-ED
Alpha-Particle-Induced Soft Error Rate in VLSI Circuits
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1982
- IEEE Journal of Solid-State Circuits
IIA-1 Generalized Scaling Theory and its Application to a 1/4 Micron Mosfet Design
- G. Baccarani
- M.R. Wordeman
- et al.
- 1982
- IEEE T-ED
A 34 µ m2 DRAM Cell Fabricated with a 1 µm Single-Level Polycide FET Technology
- Hu H. Chao
- Robert H. Dennard
- et al.
- 1981
- IEEE Journal of Solid-State Circuits