Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- Balaji Jayaraman
- Sneha Gupta
- et al.
- 2012
- ICICDT 2012
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49 results for P. Agnello
Access transistor design and optimization for 65/45nm high performance SOI eDRAM
- G. Wang
- P. Parries
- et al.
- 2008
- VLSI-TSA 2008
CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
Phase edge lithography for sub 0.1 μm electrical channel length in a 200 MM full CMOS process
- P. Agnello
- T. Newman
- et al.
- 1995
- VLSI Technology 1995
A high performance 0.15 μm CMOS
- G. Shahidi
- J. Warnock
- et al.
- 1993
- VLSI Technology 1993
A SiGe-base PNP ECL circuit technology
- D.L. Harame
- J.H. Comfort
- et al.
- 1993
- VLSI Technology 1993
Atmospheric pressure chemical vapor deposition of Si and SiGe at low temperatures
- T.O. Sedgwick
- P. Agnello
- 1992
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films