Performance enhancement on sub-70 nm strained silicon SOI MOSFETS on ultra-thin thermally mixed strained silicon/SiGe on insulator(TM-SGOI) substrate with raised S/D
- B.H. Lee
- A.C. Mocuta
- et al.
- 2002
- IEDM 2002
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49 results for P. Agnello
Process requirements for continued scaling of CMOS - The need and prospects for atomic-level manipulation
- Paul D. Agnello
- 2002
- IBM J. Res. Dev
Thickness measurement of ultra-thin gate dielectrics under inversion condition
- W. Zhu
- Mukesh Khare
- et al.
- 2001
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl μ/m CMOS technology
- H. Wong
- R. Chang
- et al.
- 1998
- IEEE Transactions on Electron Devices
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance
- Keith A. Jenkins
- Joachim N. Burghartz
- et al.
- 1996
- IEEE Transactions on Electron Devices
High-performance 0.08 μm CMOS
- L. Su
- S. Subbanna
- et al.
- 1996
- VLSI Technology 1996
Phase edge lithography for sub 0.1 μm electrical channel length in a 200 MM full CMOS process
- P. Agnello
- T. Newman
- et al.
- 1995
- VLSI Technology 1995
Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors
- P. Agnello
- V.P. Kesan
- et al.
- 1994
- Journal of Electronic Materials