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32 results for Joseph S. Newbury

First demonstration of high-Ge-content strained-Si_1-xGe_x (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications
- - Pouya Hashemi
  - Karthik Balakrishnan
  - et al.
- 2014
- IEDM 2014
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- - Sarunya Bangsaruntip
  - K. Balakrishnan
  - et al.
- 2013
- IEDM 2013
Ultra low contact resistivities for CMOS beyond 10-nm node
- - Zhen Zhang
  - Siyuranga Obasa Koswatta
  - et al.
- 2013
- IEEE Electron Device Letters
A 0.021 μm² trigate SRAM cell with aggressively scaled gate and contact pitch
- - Michael A. Guillorn
  - Josephine Chang
  - et al.
- 2011
- VLSI Technology 2011
Development and characterization of advanced process technologies for the fabrication of crystalline-Si solar cells
- - Satyavolu S. Papa Rao
  - Kate Fisher
  - et al.
- 2010
- PVSC 2010
Effective schottky barrier lowering for contact resistivity reduction using silicides as diffusion sources
- - Zhen Zhang
  - F. Pagette
  - et al.
- 2010
- VLSI-TSA 2010
Gate-all-around silicon nanowire MOSFETs and circuits
- - Jeffrey W. Sleight
  - Sarunya Bangsaruntip
  - et al.
- 2010
- DRC 2010
Sharp reduction of contact resistivities by effective schottky barrier lowering with silicides as diffusion sources
- - Zhen Zhang
  - F. Pagette
  - et al.
- 2010
- IEEE Electron Device Letters
High performance and highly uniform metal hi-k gate-all-around silicon nanowire mosfets
- - Jeffrey W. Sleight
  - Sarunya Bangsaruntip
  - et al.
- 2010
- ECS Transactions
Hydrogen silsesquioxane-based hybrid electron beam and optical lithography for high density circuit prototyping
- - M. Guillorn
  - J. Chang
  - et al.
- 2009
- Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures