Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology
- Justin Zhu
- Katsunori Onishi
- et al.
- 2024
- IEEE MDTS 2024
Dureseti (Chidu) Chidambarrao is a recognized expert in Modeling, semiconductor R&D, Design For Manufacturability, and Design Technology Co-Optimization. Chidu is currently a Senior Technical Staff Member at IBM Research where he leads cross-functional teams in Thermal Solutions for Chiplets and Advance Packaging and device architecture components of the 2nm program. Before joining IBM Research, Chidu worked at IBM Infrastructure where he led the Product-Technology-Interactions team to help deliver P/Z chips for IBM’s mainframes for the 14, 7, and 5nm technology nodes. He developed his deep process, device, and DTCO expertise while at the IBM Semiconductor R&D Center working on the 90nm through 22nm CMOS nodes. Chidu’s technical accomplishments have been recognized with multiple awards internally at IBM, including a Corporate Award in 2022, IBM’s highest technical recognition.
Chidu has over 225 US patents, is an IBM Master Inventor for 15 years, and has 65 publications. Chidu got his B Tech from the Indian Institute of Technology, Madras and his PhD from North Carolina State University.