A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- VLSI Circuits 2017
Bio
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Publications
Encoder logic for reducing serial I/O power in sensors and sensor hubs
- Phillip Stanley-Marbell
- Pier Andrea Francese
- et al.
- 2016
- HCS 2016
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2017
- ISSCC 2017
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- ISSCC 2017
Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
CMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic
- Marcel Kossel
- Matthias Braendli
- et al.
- 2016
- Electronics Letters
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Patents
- US
- 12095473
- US
- 12088316
- DE
- 11 2019 000 181
- TW
- I850965
- GB
- 2620314
- KR
- 2672586
- CN
- ZL201980010119.8
- SG
- 11202110345X
- US
- 11916568
- JP
- 7427030
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
MB
Matthias Brändli
Digital Circuit Design
TM
Thomas Morf
Senior Research Scientist
MK
Marcel Kossel
Circuit Designer
VC
Victor Chan
Yield learning & Diag Eng Prof