A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications

Abstract

We present a scaling study on phase change memory (PCM)-ovonic threshold switches (OTS) memory cells for storage class memory (SCM) applications. For the first time, the device size effect on the electrical characteristics of OTS-PCM cells is experimentally characterized with simulation support. It is found that the SET threshold voltage (VtS) of OTS-PCM cells increases as the device area scales down because of processinduced defects, as observed from experimental measurements and demonstrated with simulations. An optimized process is proposed and experimentally verified to minimize the VtS shift issue based on wafer level characterization. More importantly, combining the measurements and simulation, the device scaling trends down to sub-10 nanometers are provided for future high density cross-point PCM (XPCM) chips.