K.A. Chao
Physical Review B
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/ebeam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
K.A. Chao
Physical Review B
Shaoning Yao, Wei-Tsu Tseng, et al.
ADMETA 2011
Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
Frank Stem
C R C Critical Reviews in Solid State Sciences