Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/ebeam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
Oliver Schilter, Alain Vaucher, et al.
Digital Discovery
U. Wieser, U. Kunze, et al.
Physica E: Low-Dimensional Systems and Nanostructures
Sang-Min Park, Mark P. Stoykovich, et al.
Advanced Materials