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Soft error rate scaling for emerging SOI technology optionsP. OldigesK. Bernsteinet al.2002VLSI Technology 2002
Characteristics and device design of sub-100 nm strained Si N- and PMOSFETsK. RimJ.O. Chuet al.2002VLSI Technology 2002
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High performance of planar double gate MOSFETs with thin backgate dielectricsE.C. JonesM. Ieonget al.2001DRC 2001
Strained Si NMOSFETs for high performance CMOS technologyK. RimS.J. Koesteret al.2001VLSI Technology 2001
Carrier mobility enhancement in strained Si-On-Insulator fabricated by wafer bondingL.J. HuangJ.O. Chuet al.2001VLSI Technology 2001
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