Three dimensional CMOS devices and integrated circuits
Meikei Ieong, Kathryn W. Guarini, et al.
CICC 2003
Double gate devices based upon the FinFET architecture are fabricated, with gate lengths as small as 30 nm. Particular attention is given to minimizing the parasitic series resistance. Angled extension implants and selective silicon epitaxy are investigated as methods for minimizing parasitic resistance in FinFETs. Using these two techniques high performance devices are fabricated with on-currents comparable to fully optimized bulk silicon technologies. The influence of fin thickness on device resistance and short channel effects is discussed in detail. Devices are fabricated with fins oriented in the 〈100〉 and 〈100〉 directions showing different transport properties.
Meikei Ieong, Kathryn W. Guarini, et al.
CICC 2003
Jakub Kedzierski, Diane Boyd, et al.
IEEE Transactions on Electron Devices
Jakub Kedzierski, Edward Nowak, et al.
IEDM 2002
David J. Frank, Robert H. Dennard, et al.
Proceedings of the IEEE